Process for the selective formation of salicide on active areas of MOS devices

ABSTRACT

Process for forming salicide on active areas of MOS transistors, each MOS transistor comprising a gate and respective source and drain regions, the source and drain regions each comprising a first lightly doped sub-region adjacent the gate and a second highly doped sub-region spaced apart from the gate. The salicide is formed selectively at least over the second highly doped sub-regions of the source and drain regions of the MOS transistors, and not over the first lightly doped sub-region.

TECHNICAL FIELD

[0001] The present invention relates to a process for the selectiveformation of salicide on active areas of MOS devices.

BACKGROUND OF THE INVENTION

[0002] In the field of semiconductor integrated circuits, it is known touse composite materials comprising silicon and a transition metal e.g.,Ti, Co and the like, called silicides, for forming layers having arelatively small resistivity.

[0003] In particular, silicides are formed on active areas of MOStransistors for reducing the resistance of source and drain diffusionregions, when these regions extend significantly.

[0004] A known method for forming a silicide layer on the active areasof MOS transistors provides for forming a gate of the transistor,comprising a gate oxide layer and a polysilicon layer, introducing inthe silicon a dopant for the formation of the source and drain diffusionregions of the transistors, and then depositing, over the whole surfaceof the silicon, a transition metal, such as Ti and Co, and performing athermal process during which the transition metal reacts with thesilicon for creating the silicide.

[0005] Since the silicide layer which forms on the active area of theMOS transistor is automatically aligned with the gate, the process iscalled “self-aligned-salicidation”, shortly “salicidation”, and thelayer thus obtained is correspondingly called “salicide”.

[0006] A drawback in the formation of salicide is due to the consumptionof part of the silicon at the interface during the reaction betweensilicon and the transition metal.

[0007] In addition, during the salicidation process part of the dopantin the underlying silicon is absorbed.

[0008] For normal MOS transistors these effects are not particularlyharmful, thanks to the substantial depth of the source and draindiffusion regions and their high doping level.

[0009] However, in some applications such as those providing forforming, by means of the “Drain-Extension” (DE) technique, N- orP-channel MOS transistors for high voltage (HV), the source and draindiffusion regions of the MOS transistors, respectively, comprise a firstregion, lightly doped and shallow, and a second region, more heavilydoped and of greater thickness, connected to the first region. For thefabrication of such transistors, after the formation of the gate arelatively small dose of dopant is introduced in the silicon,respectively of N type for the N-channel transistors and of P-type forthe P-channel ones, so as to form said first lightly doped regions ofthe source and drain diffusion regions which are automatically alignedwith the gate. Successively, a high dose of dopant, of N or P type, isselectively implanted by way of a mask covering the gate and extendingover the first lightly doped regions.

[0010] In order to form salicide over the source and drain diffusionregions of the transistors, a transition metal is then deposited overthe whole silicon surface, and there is performed a thermal process.

[0011] The salicide thus forms both over the more heavily doped anddeeper regions of the source and drain diffusion regions, where asalready mentioned it does not causes particular problems, and over themore lightly doped and shallower regions of the source and draindiffusion regions.

[0012] In such lightly doped regions, due to their low doping level andtheir small thickness, the absorption of dopant by the salicide and theconsumption of part of the silicon for the formation of salicide cancause problems, for example, the short-circuit of the salicide with thesubstrate.

SUMMARY OF THE INVENTION

[0013] An object of the present invention is that of providing a processof formation of salicide over active areas of MOS transistors,particularly of the type formed by means of the “drain-Extension”technique, allowing one to overcome the above-mentioned problems, inparticular avoiding deterioration of existing lightly doped regions ofthe source and drain diffusions regions.

[0014] In an embodiment of the present invention, there is provided aprocess for forming salicide on active areas of MOS transistors, eachcomprising a gate and respective source and drain regions comprisingeach a first lightly doped sub-region near the gate and a second highlydoped sub-region spaced apart from the gate, wherein the salicide isformed selectively only over said second highly doped sub-regions of thesource and drain regions of the MOS transistors.

[0015] The salicide is formed by depositing over the whole surface of asemiconductor wafer a layer of a transition metal, but protecting(masking) those regions of the wafer where the salicide is not to beformed, in particular the first sub-regions of the source and drainregions of the MOS transistors, in such a way as the transition metal isin contact with the silicon over said second sub-regions but not overthe first sub-regions. By submitting the wafer to a thermal process, thelayer of transition metal reacts to form the salicide only in theregions where it is deposited directly over the silicon (mono- orpoly-crystalline) while remaining unmodified in the other regions fromwhich it can be removed.

[0016] Advantageously, for depositing the transition metal over saidsecond sub-regions the same mask is used as that used for the selectiveintroduction of the dopant for the formation of the second sub-regions.

[0017] These and other features and advantages of the present inventionwill be made apparent by the following detailed description ofembodiments thereof, illustrated as non-limiting examples in the annexeddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIGS. 1 to 6 show steps of a process according to a firstembodiment of the invention both in the case of an N-channel MOSFET(FIGS. 1A-6A) and in the case of a P-channel one (FIGS. 1B-6B).

[0019]FIG. 7A shows a step of a process according to a second embodimentof the invention on an N-channel MOSFET and FIG. 7B shows the same stepof a P-channel MOSFET.

[0020]FIG. 8A shows an N-channel transistor with a gate comprising threedifferent layers to which the process of the invention has been appliedand FIG. 8B shows a P-channel transistor with a gate with three layers.

[0021]FIG. 9A shows an N-channel transistor with a gate comprising fourdifferent layers to which the process of the invention has been appliedand FIG. 9B shows a P-channel transistor with a similar structure.

[0022] FIGS. 10 to 13 show steps of a process according to a thirdembodiment of the invention, applied to an N-channel MOSFET.

[0023]FIG. 14 shows an alternative of the process of FIGS. 10 to 13.

[0024]FIG. 15 shows the use of the process of FIGS. 10 to 13 for theformation of salicide only over the gate of an N-channel MOSFET havinglightly doped source and drain regions.

[0025] FIGS. 16 to 18 show steps of a process according to a fourthembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0026] With reference to FIGS. 1A and 1B, there are shown two MOStransistors 10, 11, respectively, N-channel (FIG. 1A) and P-channel(FIG. 1B), formed according to the known technique.

[0027] For the formation of the N-channel MOS transistor 10, over a Ptype substrate or well 1, particularly with a dopant concentration ofthe order of 10²⁰ atoms/cm³, a gate 2 is formed comprising a gate oxidelayer 3 and a polysilicon layer 4.

[0028] By the definition of the gate 2, there are defined two areas 50for the formation of first lightly doped N-diffusions 5A of source anddrain regions for MOS transistor 10, obtained by means of implantationand successive diffusion of N type ions in a dose of approximately 10¹²atoms/cm².

[0029] For the formation of P channel MOS transistor 11 (FIG. 1B), overan N type substrate or well 6, there is formed (simultaneously with thatof MOS transistor 10) a gate 2 comprising the gate oxide layer 3 and thepolysilicon layer 4.

[0030] There are thus defined two areas 70 for the formation, by meansof implantation of P type ions in a dose of approximately 10¹² atoms/cm²and their successive diffusion, of further first lightly doped P− sourceand drain regions 7A.

[0031] For both the transistors 10 and 11 there are subsequently formed,by means of conventional techniques, dielectric material spacers 8 onboth sides of the gate 2.

[0032] Over the whole surface of the silicon and over said transistors10, 11, as shown in FIG. 2, there is then formed another layer ofdielectric 9, such as, e.g. SiO₂, with a thickness ranging from 200 to500 Angstroms.

[0033] With reference to FIG. 3, such a layer of dielectric 9, by meansof a mask, is then selectively etched away so as to uncover surfaceportions 120 of the first source and drain regions 5A of the N-channelMOS transistor 10. Inside said surface portions 120, there are formedimplantations of N type ions at high dose, approximately of 10¹⁵atoms/cm², so to form source and drain heavily doped N+ sub-regions 12.

[0034] In this way, there are obtained source and drain regions for theN-channel transistor 10, each one formed by a first lightly doped N−sub-regions 5 and a second more heavily doped N+ sub-regions 12.

[0035] After having performed a deposition of a layer of resist 20 toprotect the sub-regions 12 from successive implants, as shown in FIG. 4,there is performed a second masking and a successive etching foruncovering surface portions 130 of part of the source and drain regions7A, where there are performed implantations of P type ions at highdoping level, approximately 10¹⁵ atoms/cm², for forming heavily doped P+sub-regions 13 of source and drain.

[0036] In this way there are obtained source and drain regions for theP-channel transistor 11, each one composed of a first lightly doped P−sub-region 7 and a second more heavily doped P+ sub-region 13.

[0037] After having removed the resist layer 20, over the whole surfacea layer of a transition metal 14, for example Ti and Co, is deposited,as shown in FIG. 5, and a thermal process is then executed for theformation of a salicide layer 15. The salicide forms only where thetransition metal is in contact with the silicon. Over the dielectric 9no salicide is formed and the transition metal is then removed, as shownin FIG. 6. As appears from FIG. 6, the presence of the dielectric 9,formed to mask the lightly doped source and drain sub-regions 5 and 7and the gates 2 of the transistors from the implantations of ions athigh dose, is advantageously used to protect regions 5, 7 and the gates2 from salicidation. Thus, the salicidation process only happens in theheavily doped sub-regions 12, 13.

[0038] According to a preferred embodiment, shown in FIG. 7, thedielectric layer 9 may comprise a double layer, a first one of SiO₂ 19,a second one of Si₃N₄ 18, thus avoiding the direct contact between thesilicon and the nitride of said second layer 18. Also in this embodimentthe overall thickness of layer 9 ranges from about 200 to about 500Angstroms.

[0039] In an alternative embodiment, the process according to thepresent invention can also be applied to the salicidation of MOStransistors which, as shown in FIG. 8, have gates 2 each comprising, inaddition to the gate oxide layer 3 and the polysilicon layer 4, afurther dielectric layer 16 suitable, for example, for improving thelithographic definition process of the gate, so as to avoid the contactbetween the polysilicon layer 4 and the overlying dielectric layer 9used for the selective implantation of the high doses of N and P typedopants.

[0040] Similarly, in another alternative embodiment, the processaccording to the invention can be applied to the salicidation of MOStransistors in which the gates 2, as shown in FIG. 9, in addition to thegate oxide layer 3 and the polysilicon layer 4, each also comprises asilicide layer 17 formed over the polysilicon layer 4. In this latterembodiment, since salicidation 15 cannot be performed over the silicidelayer 17, each gate 2 must comprise a further dielectric layer 16covering the silicide layer 17 where the latter is not protected by thedielectric 9.

[0041] The gate 2 is thus defined leaving on the polysilicon 4 the layerof residual dielectric 16. Once the spacers 8 have been formed, theprocess according to the invention is performed.

[0042] There is thus obtained a process for the selective formation ofsalicide wherein the salicide layer is formed only over the heavilydoped N+ and P+ sub-regions of source and drain 12, 13, and not over themore lightly doped N− or P− sub-regions 5 and 7. The more heavily dopedsub-regions, due to their greater thickness and their higher dopinglevel, are much less affected than the lightly doped sub-regions bydeterioration caused by consumption of silicon during the salicidationand by absorption of dopant by the salicide. Furthermore, the processdescribed does not require additional masks, because the mask alreadyprovided for the selective implantation of the high doses of N and Ptype dopants are advantageously exploited.

[0043] Referring now to FIGS. 10 to 13, there are shown steps of aprocess according to another embodiment of the present invention,referred for simplicity to the fabrication of an N-channel MOSFET only.The extension of similar principle to a P-channel MOSFET will bestraightforward for persons skilled in the art.

[0044] After having defined the insulated gate of the MOSFET, comprisingthe gate oxide 3 and the polysilicon layer 4, and after having formedlightly doped N− source and drain regions by means of a Lightly DopedDrain (LDD) implant (N- for the N-channel MOSFETs, P- for the P-channelMOSFETs, with a dopant dose of approximately 10¹² and, respectively,10¹³ atoms/cm²), the structure shown in FIG. 10 is obtained.

[0045] A CVD (Chemical Vapor Deposited) dielectric layer 30 is thendeposited over the surface. The dielectric layer 30 can be, for example,an oxide layer formed by TEOS or a layer of nitride, and has preferablya thickness of 150 to 300 nanometers.

[0046] A photoresist mask layer 31 is then formed over the structure. Aselective etching of the dielectric layer 30 is then performed; wherethe mask layer 31 is present, the dielectric layer 30 is not removed. Asvisible from FIG. 12, the mask layer 31 leaves an N-drain sub-region 5Aof the MOSFET covered. At the source side, instead, where the mask layer31 is not present, during the etching process an insulating sidewallspacer 32 is formed.

[0047] By means of the same mask layer 31 and the spacer 32, a selectiveimplantation of a high dose of dopants (e.g., 10¹⁵ atoms/cm²) is thenperformed, so as to form heavily doped N+ source and drain portions 5B.It is to be noted that this selective implant step could as well beperformed by using a different mask formed over the structure after theremoval of the photoresist layer 31.

[0048] Then after the removal of the mask layer 31, as shown in FIG. 13,a layer of a transition metal 33 is deposited over the whole surface. Athermal process is then performed so as to form, where the transitionmetal layer is in direct contact with silicon or with polysilicon, asalicide layer, as in the first embodiment previously described.

[0049] It is to be noted that, thanks to this embodiment of theinvention, the dimension of the N− region 5A at the drain side can bevaried as desired.

[0050] In an alternative embodiment shown in FIG. 14, the dielectriclayer 30 is left over the whole polysilicon gate 4 of the MOSFET, andalso covers the N− source sub-region 5A. Thus, the salicide layer willonly be formed over the heavily doped portions 5B of the source anddrain regions of the MOSFET.

[0051] Evidently, the polysilicon layer 4 of the MOSFETs can comprise alayer of polycide, such as for example Wsi₂.

[0052] The process of FIGS. 10 to 13 also allows for preventing theformation of salicide over the source and drain regions of MOSFETs thatdo not comprise heavily doped source and drain region portions, as shownin FIG. 15. The dielectric layer 30 can cover completely the polysiliconlayer 4 or, as shown in FIG. 15, the polysilicon layer 4 can be leftexposed so that a salicide layer is formed over the polysilicon layer 4.

[0053] Another alternative embodiment of the invention is shown in FIGS.16 to 18. In this embodiment, starting from the structure shown in FIG.10. two dielectric films 34, 35 are deposited sequentially, where thetwo films preferably have different etching rates.

[0054] Then, without using any mask, the upper film 35 is etched. Theetching process is stopped when the surface of the lower dielectric film34 is reached. This can be advantageously achieved if the two films 34,35 have different etching rates. In this way, as shown in FIG. 17,dielectric sidewall spacers 36 are formed.

[0055] Then a photoresist mask layer 37 is formed over a portion of theN-drain region of the MOSFET, and the lower dielectric film 34 is etcheddown to the silicon surface where the dielectric film 34 is not coveredby either the mask layer 37 or the spacer 36. The mask layer 37 couldalso not be employed, and in this case a symmetric structure would beobtained, with the N-portion 5A at the drain side having a sameextension-of the N-portion 5A at the source side.

[0056] Then, a high dose of dopants (N type in the case of an N-channelMOSFET, P type in the case of a P-channel one) is implanted as in FIG.12, so as to obtain the structure shown in FIG. 18.

[0057] It should also be noted that the upper film 35 may notnecessarily be a dielectric film. It could as well be a conductivelayer, which can be selectively removed after the etching processesbefore or after the ion implantation steps.

[0058] Even if the invention has been described in connection withnormal N-channel and P-channel MOS transistors, it is apparent that theinvention can be similarly applied also in the case of said MOStransistors with “stacked gate” type used for example to formnon-volatile memory cells.

[0059] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. A process for forming salicide on active areas of MOS transistors,each MOS transistor comprising a gate and respective source and drainregions, the source and drain regions each comprising a first lightlydoped sub-region adjacent to the gate and a second highly dopedsub-region spaced apart from the gate wherein the salicide is formedselectively at least over said second highly doped sub-regions of thesource and drain regions of the MOS transistors, and not over said firstlightly doped sub-regions.
 2. The process according to claim 1 whereinthe salicide is formed by selectively depositing a layer of a transitionmetal, in particular Ti or Co, at least over said second sub-regions butnot over said first sub-regions of the source and drain regions of theMOS transistors, and successively making said layer of transition metalreact with the underlying silicon material by means of a thermalprocess.
 3. The process according to claim 2 wherein for the step ofselectively depositing said layer of transition metal includes formingmask means, the mask means being suitable for masking at least saidfirst sub-regions of the source and drain regions of the MOStransistors.
 4. The process according to claim 3 wherein said mask meanscomprises a same mask as used for selectively introducing dopants toform said second sub-regions of the source and drain regions of the MOStransistors.
 5. The process according to claim 4 wherein the step offorming the mask means comprises forming a protective layer andselectively removing the protective layer, so as to obtain a residualprotective layer at least over said first sub-regions of the source anddrain regions of the MOS transistors.
 6. The process according to claim5 wherein said residual protective layer is also left over said gate. 7.The process according to claim 5 wherein said protective layer comprisesa lower protective layer and an upper protective layer.
 8. The processaccording to claim 7 wherein said lower and upper protective layers havedifferent etching rates.
 9. The process according to claim 1 whereinsaid gate is formed by a silicon oxide layer, a polysilicon layer, and afurther dielectric layer.
 10. The process according to claim 1 whereinsaid gate is formed by a silicon oxide layer, a polysilicon layer, asilicide layer and a further dielectric layer.
 11. A method of formingsalicide over active areas of a MOS transistor having a gate, a sourceregion and a drain region, said method comprising: defining a lightlydoped sub-region and a highly doped sub-region of the source region;defining a lightly doped sub-region and a highly doped sub-region of thedrain region; and forming salicide over the highly doped sub-regions butnot over the lightly doped sub-regions of the respective source anddrain regions.
 12. The method of claim 11 wherein the step of formingsalicide comprises: selectively depositing a layer of transition metalat least over the highly doped sub-regions but not over the lightlydoped sub-regions of respective source and drain regions; and heatingthe MOS transistor to make the transition metal layer react withunderlying silicon of the second highly doped sub-regions of respectivesource and drain regions.
 13. The method of claim 12 wherein thetransition metal includes titanium or cobalt.
 14. The method of claim11, further comprising forming a mask suitable to mask at least thelightly doped sub-regions of the respective source and drain regions,said mask preventing salicide from being formed over the lightly dopedsub-regions and also preventing the lightly doped sub-regions from beinghighly doped.
 15. The method of claim 14 wherein the step of forming themask comprises: forming a protective layer at least over the source anddrain regions; and selectively removing the protective layer to form aresidual protective layer at least over the lightly doped sub-regions ofthe respective source and drain regions.
 16. The method of claim 15wherein the residual protective layer also covers the gate of the MOStransistor and has a thickness of about 150 to about 500 Angstrom. 17.The method of claim 15 wherein the protective layer comprises a lowerand a upper protective layer respectively having different etchingrates.
 18. The method of claim 17, further comprising: forming sidewallsof the gate during etching of the upper protective layer; and depositinga protective mask at least above the lightly doped sub-region of thedrain region.
 19. The method of claim 11 wherein the gate comprises asilicon oxide layer, a polysilicon layer, a silicide layer, and afurther dielectric layer.
 20. The method of claim 14 wherein the step offorming the mask comprises: depositing a protective layer over thesurface of the MOS transistor; depositing a mask layer over theprotective layer at least above the lightly doped sub-region of thedrain region; and selectively removing the unmasked portion of theprotective layer to form a residual protective layer at least over thelightly doped sub-region of the drain region and to form a sidewallspacer over the lightly doped sub-region of the source region, saidresidual protective layer and said sidewall spacer having differentdimensions.
 21. The method of claim 20, further comprising: implanting adopant into the highly doped sub-regions by masking the lightly dopedsub-regions; removing the mask layer; depositing a transition metal atleast over the highly doped sub-regions of the respective source anddrain regions; and forming salicide at least over the highly dopedsub-regions by heating the MOS transistor.
 22. The method of claim 14wherein the step of forming the mask comprises: depositing a protectivelayer over the surface of the MOS transistor; depositing a mask layer,said mask layer partly covering the protective layer over the gatethereby leaves an exposed region of the gate; selectively removing theprotective layer to form a residual protective layer over the source anddrain regions and partly over the gate; depositing a transition metalover the transistor; and forming salicide over the exposed gate regionby a thermal process.
 23. A semiconductor device having a gate, a sourceand a drain region wherein the source and drain regions respectivelycomprises lightly doped sub-regions adjacent to the gate and highlydoped sub-regions spaced apart from the gate, said highly dopedsub-regions being covered by salicide and said lightly doped sub-regionsbeing covered by a protective layer.
 24. The device of claim 23 whereinthe salicide are formed by a layer of transition metal includingtitanium or cobalt.
 25. The device of claim 23 wherein said protectivelayer has an upper and a lower layer having different etching rates witha total thickness of about 150 to about 500 Angstrom.
 26. The device ofclaim 23, further comprising a mask layer covering at least the lightlydoped sub-region of the drain region or a sidewall spacer covering atleast the lightly doped sub-region of the source region.